Manual
ScoutChecker User Manual
CAD ERC/DRC does not catch design-level circuit issues. ScoutChecker fills that gap.
1. Quick Start
- Create a new project
- Upload NET files (required) and BOM CSV files (optional)
- Set file types and board symbols
- Configure signal assignments if needed
- If using an FPGA, select the device in FPGA Library
- Run analysis
- View results in the browser or download as ZIP
2. Project Setup
Click "New" on the Projects page to create a project. Each project represents one circuit design (one or more boards).
| Field | Description |
|---|---|
| Name | Project name (e.g. "IEA-PCB35 MAIN") |
| Description | Optional memo |
3. File Upload
Go to "File Management" from the project page. Upload files and set their types.
| Type | Extension | Description |
|---|---|---|
NET | .net | Netlist file (OrCAD format). Required. One per board. |
BOM | .csv | Bill of Materials. Adds component values/types to analysis. |
CON | .txt | Connector mapping file. Defines inter-board connections. |
EXTCN | .txt | External connector assignments. Sets power/GND entry points. |
LIB | .txt | Library file. Pin name definitions for ICs. |
DOC | any | Documents (PDFs, specs, notes, etc.). Not used in analysis, but managed with the project and included in the results ZIP. |
Board Symbol
Each NET/BOM file needs a board symbol (e.g. MAIN, POW, PHY). This identifies which board a component belongs to in multi-board designs.
BOM Column Mapping
When uploading a BOM CSV, set the column numbers as space-separated values. Example: 4 1 4 5 7 8
| # | Field | Description |
|---|---|---|
| 1 | Designator | Reference designator column (e.g. R1, C3) |
| 2 | Type | Component type column (e.g. R, C, IC) |
| 3 | Value | Component value column (e.g. 10kΩ, 100nF) |
| 4 | Model | Part number column (e.g. GRM155R71C104K) |
| 5 | Manufacturer | Manufacturer name column |
| 6 | Populate | Populate status column (to identify unpopulated parts) |
4. Signal Assignment
Go to "Signal Assign" from the project page. Signal assignments tell ScoutChecker which nets/pins are power, ground, or signals.
| Target Type | Example | Description |
|---|---|---|
NET | GND | Assign all pins on a net |
RTYPE | C | Assign all pins of a component type |
REF | MAIN.IC1 | Assign all pins of a specific component |
PIN | MAIN.IC1.3 | Assign a specific pin |
Attributes
| Attribute | Values | Description |
|---|---|---|
cSIG | POW, GND, SIG, NC | Signal type |
cLOGIC | H, L | Logic level (H=power, L=ground) |
cVOLT | 3.3V, 5V, etc. | Voltage level |
5. Analysis
Click "Run Analysis" on the project page. The pipeline runs through these major phases:
- Parse — Read NET/BOM/CON files and build the circuit graph
- Assign — Apply signal assignments and propagate attributes
- Trace — Trace GND, VCC, and signal paths through the circuit
- Check — Detect stuck terminals, power evaluation, design rule checks
- Report — Generate HTML reports and ZIP package
Analysis runs in the background. The progress page shows real-time status.
6. Results
After analysis completes, click "View Results". The sidebar organizes files by category:
| Category | Contents |
|---|---|
| Reports | Summary, PowerEvaluation, StuckTerminals, SinglePinNets, DesignReview |
| Indexes | RefList (components), PinList (pins), NetList (nets) |
| Components | Per-component detail pages grouped by type (IC, R, C, ...) |
| Nets | Per-net detail pages |
Each component/pin page shows a path diagram — a visual trace of the GND/VCC/signal paths connected to that pin.
7. Design Review
DesignReview.html checks for common design issues that CAD ERC/DRC typically misses:
| Rule | Level | What it checks |
|---|---|---|
| I2C Pull-up | Warning | SDA/SCL nets must have a pull-up resistor connected to power |
| RESET/EN Floating | Warning | RESET/RST nets must have a pull-up or pull-down resistor |
| Power Decoupling | Info | Power nets (VCC/VDD/+xV) should have a decoupling capacitor |
Each finding includes a hint explaining why it might be a false positive (e.g. "implemented on another board").
Severity Levels
- ERROR — Must fix
- WARN — Should investigate
- INFO — For reference
8. Export / Import
Export
On the project detail page, click "Export" to download a ZIP containing all project settings and uploaded files. Use this to transfer projects between environments.
Import
On the project list page, click "Import" and select an exported ZIP file. A new project is created with all files and settings restored.
Results ZIP Structure
The ZIP downloaded from "Download ZIP" on the results page has the following structure:
| Path | Contents |
|---|---|
index.html | Top page with links to Design Review and all reports. Open this first. |
result/ | Analysis result HTML files (reports, component details, net details) |
source/ | Input files (NET, BOM, CON, DOC, etc.) and settings (project.json). This folder alone can reproduce the analysis. |
9. FPGA Library
For projects using Altera (Intel) FPGAs, the FPGA Library feature automatically integrates FPGA pin information into the analysis.
Overview
FPGA IBIS data provides the function of each pin (power, GND, JTAG, config, I/O, etc.). During analysis, this data is automatically overlaid onto matching FPGA device pins. This enables:
- Auto-generation of signal assignments for FPGA power/GND pins
- Checks for pull-up resistors on nCONFIG, MSEL, JTAG configuration pins
- Checks for decoupling capacitors on power pins
How to Use
- Open "FPGA Library" from the project sub-navigation bar
- IC/U components from the netlist are listed at the top. Components whose VALUE matches an FPGA device alias are highlighted in green
- Click the "Use This" button on a matched component to automatically set the device and symbol
- Review the pin preview and click "Generate & Apply"
- Re-run analysis to apply FPGA pin attributes
Auto-Match
The system extracts IC/U component references and VALUEs from the netlist $PACKAGES section, then matches them against FPGA device aliases.
Example: Netlist VALUE 5AGXBA3DF27 → matches alias 5AGXBA3DF27 → device 5AGXBA3_F6720 is auto-selected.
If no auto-match is found, manually select the family and device from the dropdowns.
During Analysis
Pipeline Step03c (FPGA Pin Enrichment) overlays IBIS-derived pin function data onto the matching device's pins. FPGA-specific design rules (nCONFIG pull-up, MSEL pull-up, JTAG pull-up, power decoupling, etc.) use this data for evaluation.
Supported Devices
Approximately 400 device packages are supported, including Arria V GX, Cyclone V, Cyclone V SoC, Cyclone 10 LP, and Cyclone/MAX (Legacy).
10. Design Rules JSON
Design rules are defined in JSON format. You can import/export JSON files to customize and share rules.
3-Tier Settings
| Level | Purpose | Where |
|---|---|---|
| System Defaults | Built-in rules (10 rules) | Automatic |
| User Settings | Apply to all your projects | Nav dropdown → My Design Rules |
| Project Overrides | Change for a specific project only | Project → Design Rules |
Priority: Project Overrides > User Settings > System Defaults
JSON Structure
The rule JSON is an array of rule objects. Each rule has the following structure:
{
"id": "unique_rule_id (alphanumeric + underscore)",
"name": "Display name",
"target": "net | device | pin",
"match": { match conditions },
"checks": [ array of check conditions ],
"level": "error | warning | info",
"message": "Message shown when detected",
"hint": "Hint explaining possible false positives"
}target — What to inspect
| Value | Target | Description |
|---|---|---|
net | Net | Inspects each net (signal line) in the circuit |
device | Device | Inspects each component (IC, R, C, Q, etc.) |
pin | Pin | Inspects each pin individually |
match — Target filtering
An empty object {} matches all targets. Combine the following keys to filter:
| Key | Target | Description | Example |
|---|---|---|---|
net_name_pattern | net / pin | Regex match on net name | "/^(SDA|SCL|I2C)/i" |
rtype | device | Component type (string or array) | "R" or ["Q", "TR"] |
value_pattern | device | Regex match on component value | "/^DTA/i" |
checks — Check conditions
If the array is empty, matched targets become findings directly (e.g., open pin detection).
If the array has one or more checks, targets that pass all checks are OK; targets that fail any check become NG (findings).
Check Types
1. has_component
Checks whether a specific component type is connected to the net.
| Parameter | Type | Description |
|---|---|---|
type | string | "has_component" (fixed) |
rtype | string | Component type ("R", "C", etc.) |
min_count | int | Minimum required count (usually 1) |
connected_to_signal | string | Required signal type on the other end ("POW", "GND", etc.). Optional. |
// Example: Pull-up resistor check (at least 1 R connected to power)
{"type": "has_component", "rtype": "R", "connected_to_signal": "POW", "min_count": 1}
// Example: Decoupling capacitor check
{"type": "has_component", "rtype": "C", "min_count": 1}2. pin_net_role
Checks the role (power/ground) of the net connected to a specific pin of a device.
| Parameter | Type | Description |
|---|---|---|
type | string | "pin_net_role" (fixed) |
pin_match | string | Regex for pin name |
net_role | string | "power" or "ground" |
expect | bool | true: should match / false: should not match |
// Example: PNP transistor — E should be power, C should not be power
{"type": "pin_net_role", "pin_match": "/^(E|3)$/i", "net_role": "power", "expect": true}
{"type": "pin_net_role", "pin_match": "/^(C|2)$/i", "net_role": "power", "expect": false}3. power_ground_bridge
Checks whether a resistor bridges power and ground with low resistance.
| Parameter | Type | Description |
|---|---|---|
type | string | "power_ground_bridge" (fixed) |
max_ohms | number | Threshold in ohms. Detected if at or below this value. Configurable in UI. |
// Example: Detect resistors ≤100Ω bridging power and GND
{"type": "power_ground_bridge", "max_ohms": 100}Supported resistance formats: 100, 4R7 (4.7Ω), 10k (10kΩ), 0R (0Ω), 2.2, 1M, etc.
4. net_short
Checks for dangerous electrical connections on a net. The mode specifies what to detect.
| Parameter | Type | Description |
|---|---|---|
type | string | "net_short" (fixed) |
mode | string | One of the following |
| Mode | Detects |
|---|---|
power_gnd_short | Power and GND directly connected on the same net |
mixed_voltage | Different voltage power pins on the same net |
output_collision | Multiple output drivers on the same net (passive components excluded) |
{"type": "net_short", "mode": "power_gnd_short"}
{"type": "net_short", "mode": "mixed_voltage"}
{"type": "net_short", "mode": "output_collision"}Full Example: Custom Rules
[
{
"id": "spi_pullup",
"name": "SPI CS Pull-up",
"target": "net",
"match": {"net_name_pattern": "/(CS|SS|NSS)/i"},
"checks": [{"type": "has_component", "rtype": "R", "connected_to_signal": "POW", "min_count": 1}],
"level": "warning",
"message": "SPI CS line has no pull-up resistor",
"hint": "Floating CS during idle may cause unintended bus activity"
},
{
"id": "crystal_caps",
"name": "Crystal Load Capacitors",
"target": "net",
"match": {"net_name_pattern": "/(XTAL|OSC|X1|X2)/i"},
"checks": [{"type": "has_component", "rtype": "C", "min_count": 1}],
"level": "info",
"message": "No load capacitor found on crystal oscillator net",
"hint": "Not needed if the IC has internal load capacitors"
}
]Import your custom JSON file using the "Import" button on the Design Rules settings page.