Upload your netlist and BOM. Get power/GND/signal path analysis, design rule checks, and version control. Catch design issues that CAD ERC can't.
Design quality depends heavily on reviewer experience.
ERC only checks basic pin connections. It can't verify power path validity or logic level consistency.
Only experienced engineers catch subtle issues. Checklists help but can't cover everything.
When a netlist changes, understanding the full impact requires re-checking all connections.
Parses netlists into structured pin/net/component data. Auto-links with BOM.
BFS from power ICs and connectors through passive components. Auto-propagates voltage attributes.
Customizable rule sets with 3-tier hierarchy (system/user/project). Auto-detects design issues.
Auto-generates FPGA pin libraries from IBIS files. I/O standard and voltage-aware analysis.
Commit-based tracking of netlist changes. Diff view and restore to any point in time.
Compare analysis results before and after netlist changes. See new/resolved findings at a glance.
Drag & drop netlist (.net) and BOM (.csv)
Set power/GND assignments, FPGA selection, design rules
One-click full analysis. Completes in seconds
Finding list, path view, HTML/ZIP report export
The legacy desktop version is still available for existing users. New features are developed exclusively for the Web version going forward.
Legacy Windows batch analysis tool. Supports basic netlist analysis and HTML/ZIP report output.
Free account with full access to all features.
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